Title :
Performance and reliability improvement in poly-Si TFTs by fluorine implantation
Author :
Maegawa, S. ; Ipposhi, T. ; Maeda, S. ; Nishimura, H. ; Ichiki, T. ; Ashida, M. ; Tanina, O. ; Inoue, Y. ; Nishimura, T. ; Tsubouchi, N.
Author_Institution :
ULSI Lab., Mitsubishi Electr. Corp., Hyogo, Japan
Abstract :
High-performance and high-reliability TFTs were obtained using a fluorine ion implantation (FII) technique. The FII into the TFT gate poly-Si caused a positive Vth shift, increased the on current and decreased the leakage current significantly. Our investigation indicates that the Vth shift originates from negative charges generated in the gate oxide by the FII. The improvement of drain current are attributed to F passivation of trap states in the poly-Si and a modulation of offset potential due to the same negative charges under the offset region. Furthermore, high endurance for -BT stress and TDDB of the gate oxide was achieved by the FII. We consider that the strong Si-F bonds created by the FII raise the stress immunity.<>
Keywords :
SRAM chips; ion implantation; liquid crystal displays; metal-insulator-semiconductor devices; passivation; reliability; thin film transistors; F implantation; F passivation; LCD; MOS capacitors; SRAM chips; Si; TFT gate poly-Si; drain current; fluorine ion implantation technique; gate oxide; high endurance; high-performance; leakage current; negative charges; offset potential; offset region; on current; poly-Si TFTs; positive Vth shift; reliability; stress immunity; strong Si-F bonds; trap states; Crystallization; Electrodes; Grain boundaries; Hydrogen; Ion implantation; MOS capacitors; Passivation; Silicon; Stress; Thin film transistors;
Conference_Titel :
Electron Devices Meeting, 1993. IEDM '93. Technical Digest., International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-1450-6
DOI :
10.1109/IEDM.1993.347403
