A high capacitive-coupling ratio (HiCR) cell for 3 V-only 64 Mbit and future flash memories

Author

Hisamune, Y.S. ; Kanamori, K. ; Kubota, T. ; Suzuki, Y. ; Tsukiji, M. ; Hasegawa, E. ; Ishitani, A. ; Okazawa, T.

Author_Institution

ULSI Device Dev. Lab., NEC Corp., Sagamihara, Japan

fYear

1993

fDate

5-8 Dec. 1993

Firstpage

19

Lastpage

22

Abstract

A novel contactless cell with high capacitive-coupling ratio (HiCR) of 0.8, which is programmed and erased by Fowler-Nordheim tunneling, has been developed for 3 V-only 64 Mbit and future flash memories. A 1.50 /spl mu/m/sup 2/ cell area is obtained by using a 0.4 /spl mu/m technology. The HiCR cell structure is realized by 1) self-aligned definition of small tunneling regions underneath the floating-gate side wall and 2) advanced rapid thermal process for 7.5-nm thick tunnel oxynitride. The internal voltages used for program and erase are +8 V and +12 V, respectively. The total process-step numbers can be reduced to 85% compared to reported memory cells so far.<>

Keywords

CMOS integrated circuits; capacitance; integrated memory circuits; memory architecture; tunnelling; 0.4 /spl mu/m technology; 0.4 mum; 1.5 mum; 12 V; 3 V; 3 V-only; 64 Mbit; 7.5 nm; 8 V; Fowler-Nordheim tunneling; HiCR cell structure; contactless cell; erased; flash memories; floating-gate side wall; high capacitive-coupling ratio; high capacitive-coupling ratio cell; internal voltages; memory cells; programmed; rapid thermal process; self-aligned definition; small tunneling regions; total process-step numbers; tunnel oxynitride; Application software; Breakdown voltage; Capacitance; Dielectrics; Flash memory; Handheld computers; Nonvolatile memory; Rapid thermal processing; Silicon; Tunneling;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1993. IEDM '93. Technical Digest., International

Conference_Location

Washington, DC, USA

ISSN

0163-1918

Print_ISBN

0-7803-1450-6

Type

conf

DOI

10.1109/IEDM.1993.347408

Filename

347408