On the high-throughput implementation of RIPEMD-160 hash algorithm

Author

Knezzevic, M. ; Sakiyama, K. ; Lee, Y.K. ; Verbauwhede, I.

Author_Institution

ESAT/COSIC & IBBT, Katholieke Univ. Leuven, Leuven

fYear

2008

fDate

2-4 July 2008

Firstpage

85

Lastpage

90

Abstract

In this paper we present two new architectures of the RIPEMD-160 hash algorithm for high throughput implementations. The first architecture achieves the iteration bound of RIPEMD-160, i.e. it achieves a theoretical upper bound on throughput at the micro-architecture level. The second architecture is designed by performing a gate level optimization and achieves a better performance than the first one at the cost of a larger gate area. Throughputs of 3.122 Gbps and 624 Mbps are achieved, with and without pipelining, respectively.

Keywords

cryptography; field programmable gate arrays; FPGA; RIPEMD-160 hash algorithm; bit rate 3.122 Gbit/s; bit rate 624 Mbit/s; gate level optimization; micro-architecture level; Algorithm design and analysis; Authentication; Cost function; Design optimization; Digital signatures; Field programmable gate arrays; Microarchitecture; Pipeline processing; Throughput; Upper bound; DFG; FPGA; RIPEMD-160; efficient implementation; hash algorithm; retiming; throughput optimal design;

fLanguage

English

Publisher

ieee

Conference_Titel

Application-Specific Systems, Architectures and Processors, 2008. ASAP 2008. International Conference on

Conference_Location

Leuven

ISSN

2160-0511

Print_ISBN

978-1-4244-1897-8

Electronic_ISBN

2160-0511

Type

conf

DOI

10.1109/ASAP.2008.4580159

Filename

4580159