DocumentCode

2316668

Title

A compilable binary tree parallel multiplier designed for speed and testability

Author

Venzl, G. ; Mitchell, R.

Author_Institution

Siemens AG, Corporate Laboratories for Information Technology

fYear

1988

fDate

0-0 1988

Firstpage

93

Lastpage

94

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1988. Digest of Technical Papers., 1988 Symposium on

Conference_Location

Tokyo, Japan

Type

conf

DOI

10.1109/VLSIC.1988.1037439

Filename

1037439