Dual-stage hardware architecture of on-line clustering with high-throughput parallel divider for low-power signal processing

Different from previous works that focus on the iterative clustering algorithm, a dual-stage hardware architecture that supports two kinds of moving averages for the on-line clustering algorithm is proposed. The architecture includes a set of memories that operates in ping-pong mode, so that distance computations and centroid updating can be processed in pipeline. The high-throughput parallel divider in the moving-average engine is a new solution to reduce the overhead of divisions to only 1 clock cycle and to calculate cumulative moving averages with no precision loss. The experiments show that when the operating frequency is 400MHz, the gate count and the average power consumption are 16K and 6.02mW, respectively. The normalized power consumption of this work is the lowest among previous works.