Building-cell design methodology for high-speed GaAs standard-cell LSIs

Author

Sasaki, Tadahiro ; Kawakyu, Kastue ; Seshita, Toshiki ; Kameyama, Atsushi ; Terada, Toshiyuki ; Kitaura, Yoshiaki ; Uchitomi, Naotaka ; Toyoda, Nobuyuki

Author_Institution

Toshiba Corp., Kawasaki, Japan

fYear

1990

fDate

13-16 May 1990

Abstract

A novel layout concept of Building-Cell (BC) methodology which realizes high-speed GaAs standard-cell LSIs is introduced. This methodology reduces the layout area and wiring-length, and leads to a large degree of freedom for cell placement. A GaAs data bus LSI, consisting of 3500 gates and a 75-bit register file, was designed to verify the effectiveness of this methodology, which functioned at a fast cycle time of 7 ns

Keywords

III-V semiconductors; cellular arrays; circuit layout CAD; digital integrated circuits; gallium arsenide; integrated circuit technology; large scale integration; 7 ns; GaAs; area reduction; building cell design methodology; cell placement; cycle time; data bus LSI; degree of freedom; layout area; layout concept; register file; semiconductors; standard-cell LSIs; wiring length reduction; Application specific integrated circuits; Capacitance; Delay effects; Design methodology; Gallium arsenide; Large scale integration; Propagation delay; Routing; Shift registers; Ultra large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990

Conference_Location

Boston, MA

Type

conf

DOI

10.1109/CICC.1990.124752

Filename

124752