On designing a reconfigurable fault-tolerant pyramid tree network architecture

A new dynamically reconfigurable modular approach for pyramid tree network architecture is presented. A module, in which three primary processing elements (PEs) are supported by a spare processing element (SP), can be considered as a basic building block and it perfectly suits the VLSI design methodology in forming the complete fault-tolerant pyramid tree. Reconfiguration of the PEs is simple and local to the module. Since SPs can be shared across the module boundaries, multiple PE failures in a module can be tolerated. It is also shown that in addition to PE failures, this design can tolerate up to a certain extent SP failures as well. A switch structure, a simple reconfiguration algorithm, and a VLSI layout of the design are also presented. The reliability analysis shows a substantial increase in the system reliability of the proposed design over the nonredundant architecture. A yield analysis comes up with a promising result regarding single-chip implementation of the pyramid tree