An area-efficient, standard-cell based on-chip NMOS and PMOS performance monitor for process variability compensation

A completely-digital, on-chip performance monitor circuit is newly proposed. In addition to a traditional ring-oscillator, the circuit has a special buffer-line whose output duty ratio is emphasized by the difference in performance between NMOS and PMOS transistor. Thus the performance of NMOS and PMOS transistor can be estimated independently. As the monitor is designed with area-efficient by standard-cells only, it can be used widely. To demonstrate the accuracy of performance estimation and the usability of the monitor, we have fabricated the monitor in 90nm CMOS process. The estimation errors of the drain saturation current of NMOS and PMOS transistors are 2.0% and 3.4%, respectively. We also successfully reduced the output amplitude variation of D/A converter to 50% by the calibration with the estimated results by using the monitor.