Partial reconfiguration in Xilinx Virtex FPGAs: Pitfalls and solutions for SoC implementations

Recent enhancements to the Programmable Logic Device have given rise to the System-on-Chip solution, where several logically distinct modules making up an entire system exist within the same device, negating the need for specific interface technologies and allowing hardware usage to become ever more efficient. There is however, a deficiency of design tools and principles specifically targeted toward the efficient adaptation of these modules. In the mobile communication industry particularly, where the trend is to support an ever-increasing range of protocols and standards, the ability to change the functionality of hardware in a fast and efficient manner whilst maximising hardware usage efficiency has become a major hurdle. In this paper, new Field Programmable Gate Array modular design techniques are used to create structures for the design and implementation of individual System-on-Chip modules, which provide support for partial run-time reconfiguration. These structures are then used to show how the major obstacle in the implementation of Field Programmable Gate Array System-on-Chip solutions can be overcome.