• DocumentCode
    2317326
  • Title

    Circuit design of a 9ns-HIT-delay 32K byte cache macro

  • Author

    Nogami, K. ; Sakurai, T. ; Sawada, K. ; Sakaue, K. ; Miyazawa, Y. ; Tanaka, S. ; Hiruta, Y. ; Katoh, K. ; Takayanagi, T. ; Shirotopi ; Itoh, Y. ; Uchma ; Hzuka

  • Author_Institution
    Toshiba Corp.
  • fYear
    1989
  • fDate
    25-27 May 1989
  • Firstpage
    45
  • Lastpage
    46
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits, 1989. Digest of Technical Papers., 1989 Symposium on
  • Conference_Location
    Kyoto, Japan
  • Type

    conf

  • DOI
    10.1109/VLSIC.1989.1037482
  • Filename
    1037482
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2317326