The WASP 2 WSI massively parallel processor demonstrators

Author

Jalowiecki, Ian Jalowiecki ; Hedge, Stephen

Author_Institution

Brunel Univ., Uxbridge, UK

fYear

1990

fDate

13-16 May 1990

Abstract

WASP 1 is reviewed, and the WASP 2a and WASP 2b wafer-scale integration (WSI) massively parallel processor technology demonstrators, implemented in standard CMOS technology, are discussed. These latter devices are defect-tolerant arrays of 864 and 6048 processing elements and integrate 1.26 M transistors (4 cm×4 cm) and 7.87 M transistors (10 cm×10 cm). The two variants (WASP 2a and WASP 2b) are examples of the associative string processor (ASP) architecture, developed at Brunel University. WASP 2a/2b, as well as their successful predecessor, WASP 1, are the technology demonstrators of the UK Alvey WSI program

Keywords

CMOS integrated circuits; VLSI; microprocessor chips; multiprocessing systems; parallel architectures; parallel machines; 10 cm; 4 cm; Brunel University; UK Alvey WSI program; WASP; WASP 1; WASP 2; WASP 2a; WASP 2b; WSI associative string processors; WSI massively parallel processor demonstrators; associative string processor; defect-tolerant arrays; standard CMOS technology; technology demonstrators; wafer-scale integration; Application specific processors; CMOS technology; Circuit faults; Communication system control; Computer buffers; Image processing; Logic testing; Paper technology; Reconfigurable logic; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990

Conference_Location

Boston, MA

Type

conf

DOI

10.1109/CICC.1990.124758

Filename

124758