Abstract :
High-frequency digital, mixed-signal, and RF IC design demands accurate full- wave analysis for pre-layout design optimization and post-layout performance verification. However, traditional full-wave modeling techniques suffer from the well-known problems of large memory requirement and long CPU run time. Although efficient algorithms have been studied to mitigate this problem, very large-scale IC design (1) demands very large-scale electromagnetic (EM) solutions, which cannot be offered by many current computational EM techniques, and (2) imposes many unique modeling challenges that are totally new to the EM community. Therefore, it is of critical importance to develop high-capacity EM methods amenable for ICs to drive continual VLSI revolution. In (D. Jiao et al., 2007 and 2006), a layered finite element method was developed for high-frequency modeling of large-scale three-dimensional on-chip circuits. The method is shown to possess a high capacity to solve large-scale IC problems. In this paper, we propose a reduction recovery algorithm to further improve the capability of the layered finite element method. Given the solution in one layer, this algorithm can recover the solutions in other layers. In addition, the recovery scheme only involves single-layer computational complexity. Its validity has been demonstrated by numerical experiments.
Keywords :
VLSI; computational complexity; finite element analysis; integrated circuit layout; radiofrequency integrated circuits; VLSI; frequency-domain layered finite element analysis; high-capacity EM methods; large-scale high-frequency integrated circuits; reduction recovery algorithm; single-layer computational complexity; Algorithm design and analysis; Digital integrated circuits; Finite element methods; Frequency domain analysis; Integrated circuit modeling; Large scale integration; Large-scale systems; Performance analysis; Radio frequency; Radiofrequency integrated circuits;
