IRIS: a 20 MHz Image Recognition Integrated System

Author

Maguire, G. ; Brien, J. ; Finnerty, M. ; Daly, J. ; Mitchell, S. ; Rida, N. ; Riordan, J. ; Griffin, F.

Author_Institution

Silicon & Software Syst., Dublin, Ireland

fYear

1990

fDate

13-16 May 1990

Abstract

A high-performance image-processing chip with an architecture optimized for pattern recognition is described. This is the first VLSI device which integrates a complete pattern recognition system on a single chip including line delay circuitry. The full custom 1.5 μm CMOS circuit contains 250000 transistors and operates at an image sampling rate of 20 MHz. The chip die size is 12.7 mm×11.5 mm and is packaged in a 144 pin ceramic PGA. The maximum clock speed is 20 MHz, and the chip dissipates a maximum of 1.5 W

Keywords

CMOS integrated circuits; VLSI; computerised pattern recognition; computerised picture processing; 1.5 W; 1.5 micron; 12.7 mm; 144 pin package; 20 MHz; CMOS circuit; IRIS; Image Recognition Integrated System; VLSI device; architecture optimized for pattern recognition; ceramic PGA; chip die size; clock speed; complete pattern recognition system; full custom; high-performance image-processing chip; image sampling rate; line delay circuitry; power dissipation; single chip; Ceramics; Circuits; Clocks; Delay lines; Electronics packaging; Image recognition; Image sampling; Iris; Pattern recognition; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990

Conference_Location

Boston, MA

Type

conf

DOI

10.1109/CICC.1990.124763

Filename

124763