Embedded system synthesis by timing constraints solving

The paper presents an approach to embedded system synthesis which minimizes a system cost while implementing given timing requirements. The embedded system is represented by a set of finite domain constraints defining different requirements on process timing, system resources and interprocess communication. The assignment of processes to processors and interprocess communications to buses as well as their scheduling are then defined as an optimization problem. A prototype system, based on constraint solving techniques, has been implemented in CHIP 5, the constraint logic programming system. Experimental results show that this approach can be efficiently used to define different system constraints and generate optimized system implementations