Detection and reduction of via faults

Author

Wolansky, D. ; Bauer, J. ; Haak, U. ; Höppner, W. ; Katzer, J. ; Kulse, P. ; Mai, A. ; Rücker, H. ; Scheit, A. ; Schulz, K.

Author_Institution

IHP, Frankfurt, Germany

fYear

2012

fDate

24-26 Sept. 2012

Firstpage

203

Lastpage

205

Abstract

A methodology for fast detection of via faults is presented. Defective vias in large via chains are detected by subsequent use of a parametric tester for resistance measurements, a CD-SEM for voltage contrast inspection and defect localization, and focused ion beam (FIB) preparation for failure analysis. Short loop experiments were applied to fabricate large via chains in a short cycle time. The method was applied for optimizing the lithography process for via layers. As a result, the density of yield-limiting blob defects was reduced.

Keywords

electric resistance measurement; failure analysis; fault diagnosis; focused ion beam technology; inspection; lithography; semiconductor device testing; CD-SEM; FIB; defect localization; defective vias; failure analysis; fault detection; fault reduction; focused ion beam; lithography process; parametric tester; resistance measurement; via chains; via fault; via layers; voltage contrast inspection; yield-limiting blob defect; Electrical resistance measurement; Random access memory; Time measurement; SRAM; blob defects; via chain; voltage contrast; yield;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Conference Dresden-Grenoble (ISCDG), 2012 International

Conference_Location

Grenoble

Print_ISBN

978-1-4673-1717-7

Type

conf

DOI

10.1109/ISCDG.2012.6360019

Filename

6360019