Estimation of power dissipation in CMOS combinational circuits

Author

Devadas, Srinivas ; Keutzer, Kurt ; White, Jacob

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA

fYear

1990

fDate

13-16 May 1990

Abstract

It is shown that a simplified model of power dissipation relates maximizing dissipation to maximizing gate output activity, appropriately weighted to account for differing load capacitances. To find the input or input sequence that maximizes the weighted activity, algorithms are given for transforming the problem to a weighted max-satisfiability problem, and then exact and approximate algorithms for solving weighted max-satisfiability are given. That is, transformations are presented that convert a logic description into a multiple-output Boolean function of the input vector or vector sequence, where each output of the Boolean function is associated with a logic gate output transition. Algorithms for constructing the Boolean function for dynamic CMOS and static CMOS, which take into account dissipation due to glitching, are presented. Finally, efficient exact and approximate methods for solving the generated weighted max-satisfiability problem are presented

Keywords

Boolean functions; CMOS integrated circuits; combinatorial circuits; combinatorial switching; integrated logic circuits; logic design; CMOS combinational circuits; dissipation model; dynamic CMOS; glitching; input vector; load capacitances; logic gate output transition; multiple-output Boolean function; power dissipation; static CMOS; vector sequence; weighted max-satisfiability problem; Boolean functions; CMOS logic circuits; Circuit simulation; Combinational circuits; Jacobian matrices; Logic devices; Logic gates; Power dissipation; Power generation; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990

Conference_Location

Boston, MA

Type

conf

DOI

10.1109/CICC.1990.124782

Filename

124782