DocumentCode
2321215
Title
Timing issues in system-level design
Author
Dasdan, Ali ; Gupta, Rajesh K.
Author_Institution
Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
fYear
1998
fDate
16-17 Apr 1998
Firstpage
124
Lastpage
129
Abstract
We present our view of the high-level timing issues in the design and validation of embedded real-time systems. We first define the derivation problem: the problem of deriving internal timing constraints from external timing constraints in an embedded real-time system. We then give a comprehensive classification of timing constraints, discuss the state of the art on high-level system modeling and on the timing constraint derivation techniques. We finally give some pointers for future research
Keywords
high level synthesis; real-time systems; timing; embedded real-time systems; high-level system modeling; high-level timing issues; internal timing constraints; system-level design; Actuators; Embedded system; Life testing; Modeling; Real time systems; Resource management; Sensor systems; System testing; System-level design; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI '98. System Level Design. Proceedings. IEEE Computer Society Workshop on
Conference_Location
Orlando, FL
Print_ISBN
0-8186-8448-8
Type
conf
DOI
10.1109/IWV.1998.667136
Filename
667136
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