DocumentCode
2321455
Title
A sub-10 ns cache SRAM for high performance 32 bit microprocessors
Author
Reese, Ed ; Huang, Eddy
Author_Institution
VLSI Technol. Inc., San Jose, CA, USA
fYear
1990
fDate
13-16 May 1990
Abstract
A high speed cache SRAM with an output enable access time of 8 ns has been built using a 0.9 μm CMOS technology. The cache memory is configurable and can be used as either an 8K×16 in the direct mapped mode, or in a two-way set-association mode as a 2×4K×16 memory for higher cache hit rates. The cache SRAM works directly with the 82385 cache controller from Intel in a 33 MHz 80386 system. A high-speed static RAM designed to provide an easy-to-implement cache memory for high-performance microcomputers is described
Keywords
CMOS integrated circuits; SRAM chips; buffer storage; 0.9 micron; 128 kbit; 32 bit microprocessors; 33 MHz; 8 ns; 80386 system; 82385 cache controller; CMOS technology; Intel; cache SRAM; configurable memory; direct mapped mode; high speed cache; high-performance microcomputers; output enable access time; static RAM; two-way set-association mode; CMOS technology; Cache memory; Control systems; Job design; Latches; Microcomputers; Microprocessors; Random access memory; Read-write memory; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990
Conference_Location
Boston, MA
Type
conf
DOI
10.1109/CICC.1990.124786
Filename
124786
Link To Document