Title :
NAP (no ALU processor): the great communicator
Author :
Fried, Jeff ; Kuszmaul, Bradley C.
Author_Institution :
MIT Lab. for Comput. Sci., Cambridge, MA, USA
Abstract :
A processor chip for use in massively parallel computer called the no ALU (arithmetic and logic unit) processor (NAP) is described. This processor is an experimental design incorporating several architectural features which make it simple to program, general-purpose, and efficient. The arithmetic functions normally performed by an ALU are instead performed by table lookups into memory. In addition, a very flexible programming model is provided, which supports indirect addressing and multiple concurrent instructions while operating in a single-instruction multiple-data (SIMD) or multiple-SIMD (MSIMD) mode. The instruction set architecture of the NAP and the processor design and the implementation of the NAP chip are discussed. The NAP is evaluated, and the lessons learned from this project are summarized
Keywords :
microprocessor chips; parallel machines; NAP; flexible programming model; indirect addressing; instruction set architecture; massively parallel computer; multiple concurrent instructions; multiple-SIMD; processor chip; single-instruction multiple-data; table lookups; Buildings; Computer networks; Concurrent computing; Hardware; Laboratories; Logic design; Multiprocessor interconnection networks; Process design; Routing; Table lookup;
Conference_Titel :
Frontiers of Massively Parallel Computation, 1988. Proceedings., 2nd Symposium on the Frontiers of
Conference_Location :
Fairfax, VA
Print_ISBN :
0-8186-5892-4
DOI :
10.1109/FMPC.1988.47458
