Title :
Design of VLSI switch for highly parallel multiprocessor system
Author :
Hsu, Yarsicn ; Benveniste, C. ; Ruedinger, J. ; Tan, C.
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
The design of a large, multistage interconnection network that has been successfully constructed and used in a version of the RP3 system is described. The network hardware is scalable and can be used for systems consisting of anywhere from four to hundreds of processor and memory elements. An overview is given of the switch architecture, followed by the packaging structure. A description of the methodology used for logic design and verification of the large silicon chip is presented
Keywords :
CMOS integrated circuits; VLSI; digital integrated circuits; logic design; multiprocessor interconnection networks; packaging; parallel processing; CMOS switching chip; RP3 system; VLSI switch; highly parallel multiprocessor system; logic design; multistage interconnection network; packaging structure; switch architecture; Concurrent computing; Delay; Educational institutions; Logic design; Multiprocessing systems; Packet switching; Parallel processing; Routing; Switches; Very large scale integration;
Conference_Titel :
Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990
Conference_Location :
Boston, MA
DOI :
10.1109/CICC.1990.124788
