Abstract :
The nonvolatile semiconductor memory (NVSM) technical community has witnessed great progress in the past four decades, and is currently looking at the challenge of finding specific technologies that will be compatible with nano-scale CMOS. In this brief review, efforts to explore new memory alternatives was examined in historical context, and an invitation was extended for volunteers to provide inputs to this project. Nonvolatile semiconductor memory (NVSM) is going through transitions in technology and in market applications that require examination of alternative approaches. In the background of this ongoing competition is the International Technology Roadmap for Semiconductors (ITRS). The ITRS outlines the boundary conditions and parameters for successive generations of memory capable of maintaining historical growth rates for density. The ITRS, that once tracked only a few parameters for flash memory, has expanded the depth of coverage for flash and is now including a number of alternative technologies. In addition, a relatively new portion of the ITRS is devoted to emerging research devices (ERD). The ERD attempts to identify technologies that are in the research stage of maturity and examine whether those technologies have the potential to play a part in the integrated circuit systems that are expected to appear after the anticipated breakdown of conventional CMOS scaling. While this dynamic is a leading edge subject commanding the attention of a world wide community of technologists, it is not true that the task is entirely new; there are many similarities in the history of NVSM to the present situation. Looking back at the issues and state of research and development over the past five decades reveals that we solve what appears to be the same problem over and over again. The difference is that we approach these problems in the context of the current state of technology, and each re-invention of the wheel represents a new set of compromises to achieve practical systems. The tabulations and discussions presented in the ITRS are a composite of technical inputs from many highly qualified individuals. The mechanics of how this information is developed was described. This is to some extent a volunteer effort, and the participation of additional scie- ntists and engineers is sought in the model developments and critiques for individual NVSM technologies. Interested persons are encouraged to express willingness to help by sending an email message that briefly describes their technical background and specific NVSM technology expertise.
Keywords :
CMOS memory circuits; semiconductor storage; International Technology Roadmap for Semiconductors; emerging research devices; nano-scale CMOS; nonvolatile semiconductor memory; Boundary conditions; CMOS integrated circuits; CMOS technology; Electric breakdown; Flash memory; History; Integrated circuit technology; Nonvolatile memory; Research and development; Semiconductor memory;