Optimization and Implementation on Fpga of the DCT/IDCT Algorithm

Author

Atitallah, A.B. ; Kadionik, P. ; Ghozzi, F. ; Nouel, P. ; Masmoudi, N. ; Marchegay, Ph

Author_Institution

Lab. of Electron. & Inf. Technol., Nat. Eng. Sch. of Sfax

Volume

3

fYear

2006

fDate

14-19 May 2006

Abstract

In this paper, we present a comparison between two methods, the modified Loeffler algorithm (11 MUL and 29 ADD) and distributed arithmetic, to implement the DCT/IDCT algorithm for MPEG or H.26x video compression using VHDL description language. The implementation has been achieved on Altera Stratix EP1S10 FPGA which provides a dedicated DSP blocks required for common signal processing functions. A new solution based on this DSP blocks used to implement multipliers for the modified Loeffler algorithm in order to optimize speed and area

Keywords

data compression; discrete cosine transforms; distributed arithmetic; field programmable gate arrays; video coding; Altera Stratix EP1S10 FPGA; DCT-IDCT algorithm; DSP blocks; H.26x video compression; MPEG; VHDL description language; digital signal processing; discrete cosine transforms; distributed arithmetic; field programmable field arrays; modified Loeffler algorithm; Arithmetic; Computer architecture; Digital signal processing; Discrete cosine transforms; Discrete transforms; Field programmable gate arrays; Hardware; Laboratories; Signal processing algorithms; Transform coding;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech and Signal Processing, 2006. ICASSP 2006 Proceedings. 2006 IEEE International Conference on

Conference_Location

Toulouse

ISSN

1520-6149

Print_ISBN

1-4244-0469-X

Type

conf

DOI

10.1109/ICASSP.2006.1660807

Filename

1660807