Embedded ferroelectric memory using a 130-nm 5 metal layer Cu / FSG logic process

Author

Summerfelt, S. ; Aggarwal, S. ; Boku, K. ; Celii, F. ; Hall, L. ; Matz, L. ; Martin, S. ; McAdams, H. ; Remack, K. ; Rodriguez, J. ; Taylor, K. ; Udayakumar, K.R. ; Moise, T. ; Bailey, R. ; Depner, M. ; Fox, G. ; Eliason, J.

Author_Institution

Si Technol. Dev., Texas Instrum., Dallas, TX, USA

fYear

2004

fDate

15-17 Nov. 2004

Firstpage

153

Lastpage

154

Abstract

An embedded ferroelectric memory (FRAM) has been developed using a 1.5V, 130nm 5 metal layer Cu / FSG logic process. The only modification to the logic process was the addition of a ferroelectric process consisting of two additional masks (FECAP, VIA0) immediately before MET1. The ferroelectric was 70nm Pb(Zr,Ti)O3 (PZT) deposited by metalorganic chemical vapor deposition (MOCVD). The bit distribution of small ferroelectric capacitors (< 0.2 μm²) was measured after fabrication and bake. A reasonable amount of property degradation after 6000hr 125°C bake was observed.

Keywords

MOCVD; copper; embedded systems; ferroelectric storage; lead compounds; 1.5 V; 125 C; 130 nm; 6000 hrs; 70 nm; Cu; FRAM; FSG logic process; PZT; PbZrO3TiO3; bit distribution; embedded ferroelectric memory; ferroelectric capacitors; metal layer; metalorganic chemical vapor deposition; property degradation; Capacitors; Chemical vapor deposition; Degradation; Fabrication; Ferroelectric films; Ferroelectric materials; Logic; MOCVD; Nonvolatile memory; Random access memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Non-Volatile Memory Technology Symposium, 2004

Print_ISBN

0-7803-8726-0

Type

conf

DOI

10.1109/NVMT.2004.1380833

Filename

1380833