Design and test of general-purpose SPI Master/Slave IPs on OPB bus

SPI is one of the most commonly used serial protocols for both inter-chip and intra-chip low/medium speed data-stream transfers. In conformity with design-reuse methodology, this paper introduces high-quality SPI Master/Slave IPs that incorporate all necessary features required by modern ASIC/SoC applications. Based upon Motorola´s SPI-bus specifications, version V03.06, release February 2003, the designs are general purpose solutions offering viable ways to controlling SPI-bus, and highly flexible to suit any particular needs. The purpose of this paper is to provide a full description of an up-to-date SPI Master/Slave FPGA implementations. All related issues, starting from the elaboration of initial specifications, till the final system verification, are comprehensively discussed and justified. The whole design code, either for synthesis or verification, is implemented in Verilog 2001 (IEEE 1365). The RTL code is technology independent, achieving a transfer rate of 71 and 75 MBPS for the Master and the Slave, respectively, when mapped onto Xilinx´s Virtex 5 FPGA devices.