1.5-V 10-Ms/s 8-bit Pipeline ADC in 0.13 μm CMOS using metal fringe capacitor

Author

Ge, Fuding ; Kellar, Scot ; Thomas, Brent

Author_Institution

Intel Corp., Chandler, AZ

fYear

2008

fDate

Nov. 30 2008-Dec. 3 2008

Firstpage

133

Lastpage

136

Abstract

This paper presents the design and measured results of a 1.5-V 10-Ms/s 8-bit pipeline ADC in 0.13 mum CMOS technology. Since there is no MiM-cap available in this process, a specially designed metal fringe cap was used instead. The ADC can digitalize multi-channel signals through a timing-multiplexing scheme. It has rail-to-rail full scale analog input signal range capability through a rail-to-rail unity-gain buffer and a single- to differential-ended signal transformation stage. It achieves a DNL of +0.46/-0.39 LSB and INL of +0.62/-0.44 LSB with a power dissipation of 3.75 mW from a single 1.5 V power supply and a silicon area of 600 mum times 1000 mum.

Keywords

CMOS integrated circuits; analogue-digital conversion; capacitors; logic design; pipeline processing; CMOS technology; MiM-cap; analog-to-digital converter; metal fringe capacitor; multichannel signals; pipeline ADC; power 3.75 mW; rail-to-rail unity-gain buffer; signal transformation stage; size 0.13 mum; size 1000 mum; size 600 mum; timing-multiplexing scheme; voltage 1.5 V; word length 8 bit; CMOS technology; Capacitors; Circuit noise; Digital circuits; Pipelines; Power supplies; Rail to rail inputs; Signal processing; Voltage; Working environment noise;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2008. APCCAS 2008. IEEE Asia Pacific Conference on

Conference_Location

Macao

Print_ISBN

978-1-4244-2341-5

Electronic_ISBN

978-1-4244-2342-2

Type

conf

DOI

10.1109/APCCAS.2008.4745978

Filename

4745978