A 54 MHz chip set for HDTV filtering

Author

Joanblanq, C. ; Rothan, F. ; Senn, P.

Author_Institution

CNET-CNS, Meylan, France

fYear

1990

fDate

13-16 May 1990

Abstract

The HDTV European project EUREKA-95 requires complex video processing to be carried out in the encoder. A chip set optimized for large kernel 2D transversal filters, including a programmable delay line and a filter chip, is presented. They can operate at 54 MHz and have been developed in a 1.0 μm CMOS technology. The basic architecture is a modified transposed transversal filter systolic array, where an extra data bus and a 9-b adder are provided in each filter cell to handle the horizontal symmetry. Though expensive compared to a folded data bus, this structure can be pipelined to relax the timing demands for high-speed applications

Keywords

CMOS integrated circuits; delay lines; digital integrated circuits; high definition television; pipeline processing; systolic arrays; television equipment; two-dimensional digital filters; video signals; 1 micron; 54 MHz; CMOS technology; EUREKA-95; HDTV European project; HDTV filtering; chip set; complex video processing; encoder; high-speed applications; horizontal symmetry; large kernel 2D transversal filters; modified transposed transversal filter systolic array; pipelined structure; programmable delay line; Adders; CMOS technology; Circuits; Delay lines; Filtering; HDTV; Kernel; Systolic arrays; TV; Transversal filters;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990

Conference_Location

Boston, MA

Type

conf

DOI

10.1109/CICC.1990.124796

Filename

124796