Leakage power estimation and minimization in configurable logic block of FPGA

Reconfigurable architectures are well suited for wireless application since they provide high performance computation together with the capability to adapt to changing communication protocols. Moving to deep sub-micron technology and below, FPGA could suffer from leakage energy consumption. This paper estimates the extensive transistor level leakage power of Virtex-II FPGAs Configurable Logic Block (CLB) at 65 nm technology and, also explore different techniques to minimize leakage power. HSPICE simulations based on BPTM (Berkeley Predictive Technology Model) at 25degC and 85degC shows that, for worst-case data, techniques such as high threshold voltage (HV_T), high gate-oxide (HT_ox) and Gate biasing (NVGS) improve the leakage power saving by up to 65.70%, 70.53% and 31.85% with average delay penalty of 15.40%, 26.24% and 0% respectively.