DSP-based implementation of Viterbi decoder for trellis-coded 8PSK

Author

Zhigang, Cao ; Yongkun, Liao

Author_Institution

Dept. of Electron. Eng., Tsinghua Univ., Beijing, China

fYear

1990

fDate

24-27 Sep 1990

Firstpage

697

Abstract

The potential performance of four-state trellis-coded octal phase shift keying (8PSK) systems with different hardware complexities was evaluated by computer simulations. The experimental trellis coded 8PSK prototype described is designed to comply with the specification of a conventional SCPC/QPSK modem operating at a 64 kb/s data rate. To ensure full compatibility, the major filtering and IF-circuit sections of the existing SCPC/QPSK system remain unchanged. Only the QPSK modulator and demodulator are replaced with a four-state coded 8PSK encoder-modulator and demodulator-decoder. An implementation of a soft-decision Viterbi decoder for four-state trellis-coded 8PSK systems which is based on a single-chip digital signal processor is shown

Keywords

decoding; digital signal processing chips; phase shift keying; 64 kbit/s; DSP-based implementation; SCPC/QPSK modem; Viterbi decoder; demodulator-decoder; encoder-modulator; octal phase shift keying; single-chip digital signal processor; soft decision decoding; trellis-coded 8PSK; Computer simulation; Decoding; Filtering; Hardware; Modems; Modulation coding; Phase shift keying; Prototypes; Quadrature phase shift keying; Viterbi algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer and Communication Systems, 1990. IEEE TENCON'90., 1990 IEEE Region 10 Conference on

Print_ISBN

0-87942-556-3

Type

conf

DOI

10.1109/TENCON.1990.152700

Filename

152700