DocumentCode
2323692
Title
Mersenne Twister Random Number Generation on FPGA, CPU and GPU
Author
Tian, Xiang ; Benkrid, Khaled
Author_Institution
Sch. of Eng., Univ. of Edinburgh, Edinburgh, UK
fYear
2009
fDate
July 29 2009-Aug. 1 2009
Firstpage
460
Lastpage
464
Abstract
Random number generation is a very important operation in computational science e.g. in Monte Carlo simulations methods. It is also a computationally intensive operation especially for high quality random number generation. In this paper, we present the design and implementation of a parallel implementation of one of the most widely used random number generators, namely the Mersenne Twister. The latter is very widely used in high performance computing applications such as financial computing. Implementations of our parallel Mersenne Twister number generator core on Xilinx Virtex4 FPGAs achieve a throughput of 26.13 billion random samples per second. The paper also reports equivalent parallel software implementations running on an Intel Core 2 Quad Q9300 CPU with 8 GB RAM, using multi-threading technology and the Intelreg Math Kernel Library (MKL), as well as on an NVIDIA 8800 GTX GPU. Comparative results show that our FPGA-based implementation outperforms equivalent CPU and GPU implementations by ~25times and ~9times respectively. Moreover, when using the same amount of energy, the FPGA can generate 37times and 35times more Mersenne Twister random samples than the CPU and the GPU, respectively.
Keywords
field programmable gate arrays; multi-threading; random number generation; CPU; GPU; Mersenne Twister; Xilinx Virtex4 FPGA; field programmable gate arrays; financial computing; multithreading technology; number generator core; random number generation; random number generator; Adaptive systems; Application software; Central Processing Unit; Concurrent computing; Field programmable gate arrays; Graphics; Hardware; High performance computing; NASA; Random number generation; FPGA; Mersenne Twister; random number generator;
fLanguage
English
Publisher
ieee
Conference_Titel
Adaptive Hardware and Systems, 2009. AHS 2009. NASA/ESA Conference on
Conference_Location
San Francisco, CA
Print_ISBN
978-0-7695-3714-6
Type
conf
DOI
10.1109/AHS.2009.11
Filename
5325420
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