A pseudo-differential comparator-based pipelined ADC with common mode feedforward technique

Author

Ding, Li ; Chan, Sio ; Wong, Kim-Fai ; Sin, Sai-Weng ; Seng-Pan, U. ; Martins, R.P.

Author_Institution

Analog & Mixed Signal VLSI Lab., Univ. of Macau, Macau

fYear

2008

fDate

Nov. 30 2008-Dec. 3 2008

Firstpage

276

Lastpage

279

Abstract

Comparator based switched capacitor technique is a new topic because of its suitability of scaling and its inherent low power consumption. Since CBSC technique suffers from the overshoot due to the comparator delay, this paper gives a detailed analysis on the overshoot signal, and a common mode feedforward circuit is proposed to correct the overshoot error. A 10-bit 100 MS/s pseudo differential pipelined ADC is presented to verify the idea. The SNDR of the pipelined ADC is 55 dB.

Keywords

CMOS integrated circuits; analogue-digital conversion; comparators (circuits); delay circuits; feedforward; low-power electronics; pipeline processing; switched capacitor networks; CBSC technique; CMOS technology; SNDR; common mode feedforward technique; comparator based switched capacitor technique; comparator delay; low power consumption; pseudodifferential comparator-based pipelined ADC; CMOS technology; Charge transfer; Delay effects; Energy consumption; Error correction; Linearity; Logic gates; Propagation delay; Silicon compounds; Switched capacitor circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2008. APCCAS 2008. IEEE Asia Pacific Conference on

Conference_Location

Macao

Print_ISBN

978-1-4244-2341-5

Electronic_ISBN

978-1-4244-2342-2

Type

conf

DOI

10.1109/APCCAS.2008.4746013

Filename

4746013