Title :
Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Abstract :
The following topics are dealt with: fault tolerant structures; reconfiguration; physical analysis; yield modeling; design for yield; testing techniques; testable architectures; self-checking and error-correcting architectures; defect/fault tolerance in analog systems
Keywords :
fault tolerant computing; BIST; analog systems; computer architecture; defect location; defect/fault tolerance; design for yield; error-correcting architectures; fault tolerant structures; logic design; logic testing; physical analysis; reconfiguration; self-checking; testable architectures; yield modeling;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 1993., The IEEE International Workshop on
Conference_Location :
Venice, Italy
Print_ISBN :
0-8186-3502-9
DOI :
10.1109/DFTVS.1993.595592
