Power Research of JPEG Circuits in FPGA

This paper presents some power results of Joint Photographic Experts Group (JPEG) in Field-Programmable Gate Array (FPGA) and provides some analysis and results in reduced dynamics-power methods of it. The dynamic power consumed by a digital CMOS circuit is directly proportional to both switching activity and payload capacitance. We use Xilinx XPower Analyzer to analyze the impact of different switching frequency of JPEG in FPGA and optimization results. Experimental results show that the dynamic power is linear with switching frequency and reduces with glitching reducing techniques.