A design method for skew tolerant latch design

This paper describes a new design method for skew-tolerant latch design (STLD) and evaluation on a commercial chip design. The conventional edge-triggered flip-flop (FF) design methods using clock synchronization are very practical, since only the timing constraints defined by a given clock frequency are optimized. However, clock skew that has a strong influence on clock frequency design prevents the FF design because of the variations. Thus, level-triggered latch design methods have been proposed as alternatives to FF-based design methods. An STLD is a kind of level-triggered latch design in which an FF is replaced by a pair of latches: a low-level triggered latch and a high-level triggered latch, and these two latches are moved after replacement. Although STLD can improve clock skew problems, this method is very complicated. We propose a new and more general design method for STLD that uses a new latch moving method. The experimental results indicated that about 6000 timing violation points were improved by using the proposed method on a 100 K gate circuit without resulting in a large penalty area.