Implementation of a neuron dedicated to Kohonen maps with learning capabilities

A compact implementation of Kohonen-oriented neurons with learning capability, using both analog and digital techniques, with standard low-cost CMOS technologies, is described. Each synaptic weight is stored as a discrete voltage on a capacitor. Leakage currents are compensated by a special circuitry, which is also used for learning. Input signals are frequency-coded pulse streams, and the synaptic multipliers are reduced to simple AND gates