High-speed highly-linear CMOS S/H circuit

Author

Sadollahy, Mahmoud ; Hadidi, Khayrollah

Author_Institution

Azad Islamic Univ., Mashhad

fYear

2008

fDate

13-15 May 2008

Firstpage

550

Lastpage

553

Abstract

This paper describes the high-speed and highly-linear CMOS sample/hold circuit that was used in front end of an ADC. The architecture of sample/hold based on an open-loop structure that enables it operates in high speed. The sample/hold consists of highly linear open-loop buffer and bootstrapped switch. Spice simulation with 0.35-um CMOS BSIM3v3 model parameters showed the SNDR (signal to noise-distortion ratio) more than 72 dB and 64 dB for 20 MHz and 50 MHz 1 Vp-p sinusoidal inputs respectively at 200 MS/s with 3.1 mW power consumption.

Keywords

CMOS integrated circuits; SPICE; analogue-digital conversion; bootstrapping; buffer circuits; sample and hold circuits; CMOS BSIM3v3 model parameters; CMOS S/H circuit; Spice simulation; analogue-digital conversion; bootstrapped switch; high-speed circuit; highly-linear circuit; open-loop buffer; power 3.1 mW; sample/hold circuit; size 0.35 mum; Bandwidth; Capacitors; Digital signal processing; Energy consumption; Linearity; MOS devices; Microelectronics; Sampling methods; Switches; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer and Communication Engineering, 2008. ICCCE 2008. International Conference on

Conference_Location

Kuala Lumpur

Print_ISBN

978-1-4244-1691-2

Electronic_ISBN

978-1-4244-1692-9

Type

conf

DOI

10.1109/ICCCE.2008.4580664

Filename

4580664