Title :
Synchronous Digital Implementation of the AER Communication Scheme for Emulating Large-Scale Spiking Neural Networks Models
Author :
Moreno, J.M. ; Madrenas, J. ; Kotynia, L.
Author_Institution :
Dept. of Electron. Eng., Tech. Univ. of Catalunya, Spain
fDate :
July 29 2009-Aug. 1 2009
Abstract :
In this paper we shall present a fully synchronous digital implementation of the Address Event Representation (AER) communication scheme that has been used in the PERPLEXUS chip in order to permit the emulation of large-scale biologically inspired spiking neural networks models. By introducing specific commands in the AER protocol it is possible to distribute the AER bus among a large number of chips where the functionality of the spiking neurons is being emulated. A careful design of the AER encoder module using compact Content Addressable Memories (CAMs) allows for a feasible realization of large-scale models.
Keywords :
content-addressable storage; encoding; microprocessor chips; neural nets; protocols; system buses; AER bus; AER communication scheme; AER encoder module design; AER protocol; PERPLEXUS chip; address event representation; content-addressable memories; neural network emulation; spiking neural network models; synchronous digital implementation; Associative memory; Biological information theory; Biological system modeling; Emulation; Hardware; Large-scale systems; Macrocell networks; Neural networks; Neurons; Protocols;
Conference_Titel :
Adaptive Hardware and Systems, 2009. AHS 2009. NASA/ESA Conference on
Conference_Location :
San Francisco, CA
Print_ISBN :
978-0-7695-3714-6
DOI :
10.1109/AHS.2009.14
