Speeding-up wide-fan in domino logic using a controlled strong PMOS keeper

Wide fan in domino logic finds a variety of applications in microprocessors, digital signal processors, and dynamic memory. Specifically, there is a large number of applications that contain 8 or more transistors connected in parallel in the pull-down network (PDN) and thus the subthreshold leakage and charge sharing become severe. So, a strong PMOS keeper must be used in order to compensate for this leakage. However, the use of a strong keeper in the conventional domino circuit degrades the speed of the circuit considerably or results in an erroneous output. In this paper, a novel technique that acts to speed up the operation of wide fan in domino logic using a properly sized keeper is proposed. The keeper is controlled via a controlling CMOS circuit. Some design issues of this technique such as the effect of the charge sharing on the operation of the proposed circuit and the size of the PMOS keeper will be discussed in this paper. Simulation will be carried out for the 0.13 mum technology with V_DD=1.2 V for the case of 16 NMOS transistors in the PDN. Simulation results show the better noise immunity of the proposed circuit and the larger speed, however at the cost of increasing the area.