A preprogrammed artificial neural network architecture in signal processing

Author

Bloomer, J. ; Frank, P. ; Engeler, W.

Author_Institution

GE Corp. Res. & Dev., Schenectady, NY, USA

fYear

1990

fDate

13-16 May 1990

Abstract

A mask-programmable artificial neural network (ANN) chip architecture, the tile-based ANN chip assembly, test and simulation results, and use it in signal processing systems are presented. The ANN chip architecture itself is a critical portion of the development. It is presented as a tool, in an abstract fashion, and the system design it makes possible and the process by which algorithms are converted to silicon (chip floorplan, tiling, etc.) are emphasized

Keywords

computerised signal processing; neural nets; parallel architectures; chip floorplan; mask-programmable; preprogrammed artificial neural network architecture; signal processing; system design; tile-based ANN chip assembly; Adaptive systems; Artificial neural networks; Capacitors; Clocks; Convolution; Intelligent networks; Signal processing; Signal processing algorithms; Silicon; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990

Conference_Location

Boston, MA

Type

conf

DOI

10.1109/CICC.1990.124806

Filename

124806

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2324653