Design and implementation of MP3 decoder using partial dynamic reconfiguration on Virtex-4 FPGAs

Dynamic reconfiguration has always constituted a challenge for embedded systems designers. Nowadays, technological developments make possible to do it on Xilinx FPGAs, but setting up a dynamically reconfigurable system remains a painful and complicated task. This architecture can benefit from being able to load and unload modules at run-time and using this feature, significant reduction in hardware resources and power dissipation of a chip can be achieved. In this paper, the design and implementation of a MP3 decoder is presented in which IMDCT and antialias blocks are implemented as reconfigurable blocks. In this work, slice based bus macros have been designed and implemented on a XC4VLX25 FPGA using the Xilinx FPGA-Editor software. The reconfiguration time of this design is 19 ms.