DocumentCode
2324706
Title
Digital PLL with controllable frequency response time and overshoot
Author
Lin, Z. ; Wu, J. ; He, X.
Author_Institution
Zhejiang Univ., Hangzhou, China
fYear
2001
fDate
18-18 Oct. 2001
Firstpage
321
Lastpage
325
Abstract
A simple digital control scheme for phase-locked loops (PLLs) is presented. The proposed scheme can adjust control parameters automatically according to phase differences. The control system based on a digital signal processor (DSP) TMS320F240 is constructed and has been applied in uninterrupted power supply (UPS) systems. Detailed simulation and experimental results are presented.
Keywords
digital control; digital signal processing chips; frequency response; phase locked loops; uninterruptible power supplies; voltage control; TMS320F240 DSP; control parameters; controllable frequency response time; controllable overshoot; digital PLL; digital control scheme; digital signal processor; phase-locked loops; uninterruptible power supply;
fLanguage
English
Publisher
iet
Conference_Titel
Telecommunications Energy Conference, 2001. INTELEC 2001. Twenty-Third International
Conference_Location
Edinburgh, UK
ISSN
0537-9989
Print_ISBN
0-85296-744-6
Type
conf
DOI
10.1049/cp:20010617
Filename
988578
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