DocumentCode :
2324714
Title :
Sub-1V capacitor-free low-power-consumption LDO with digital controlled loop
Author :
Chen, Jiann-Jong ; Lin, Ming-Shian ; Lin, Ho-Cheng ; Hwang, Yuh-Shyan
Author_Institution :
Nat. Taipei Univ. of Technol., Taipei
fYear :
2008
fDate :
Nov. 30 2008-Dec. 3 2008
Firstpage :
526
Lastpage :
529
Abstract :
A CMOS sub-1 V capacitor-free low-power-consumption low-dropout voltage regulator (LDO) with digital controlled loop is presented in this paper. This technique can make power consumption lower than other LDOs with traditional controlled Loop. Especially, the performance of power consumption of proposed LDO without off-chip capacitors is excellent. The LDO can also be stable even without the output capacitor. With 0.9 V power supply voltage, the output voltage is designed as 0.6 V. The maximum output current of the LDO is 120 mA at an output of 0.6 V. The prototype of the LDO is fabricated with TSMC 0.35-mum CMOS processes. The chip area (including I/O pad) is only 927 mum times 969 mum.
Keywords :
CMOS digital integrated circuits; digital control; integrated circuit design; low-power electronics; voltage regulators; CMOS capacitor-free low-power LDO; current 120 mA; digital controlled loop; low-dropout voltage regulator; off-chip capacitors; size 0.35 mum; size 927 mum; size 969 mum; voltage 0.6 V; voltage 0.9 V; voltage 1 V; Batteries; Capacitors; Charge pumps; Circuits; Digital control; Energy consumption; Low voltage; Phase frequency detector; Power supplies; Voltage control;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2008. APCCAS 2008. IEEE Asia Pacific Conference on
Conference_Location :
Macao
Print_ISBN :
978-1-4244-2341-5
Electronic_ISBN :
978-1-4244-2342-2
Type :
conf
DOI :
10.1109/APCCAS.2008.4746076
Filename :
4746076
Link To Document :
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