Title :
A compact and general-purpose neural chip with electrically programmable synapses
Author :
Lee, Bang ; Sheu, Bing
Author_Institution :
Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA
Abstract :
A neural chip with 64 neurons and 4096 DRAM-like programmable synapses has been designed and fabricated in 29 mm2 area using the 2-μm scalable CMOS process from MOSIS Service. With 0.2-s refresh cycle, 8-b accuracy in synapses can be achieved for image processing. A system simulation result of image restoration using the programmable synapse chip architecture is also presented. An industrial-level 500-neuron chip with the fully connected synapse array can be implemented in 1-μm CMOS technologies
Keywords :
CMOS integrated circuits; computerised picture processing; neural nets; 1 micron; 2 micron; DRAM-like programmable synapses; MOSIS Service; electrically programmable synapses; general-purpose neural chip; image processing; image restoration; industrial-level 500-neuron chip; neurons; refresh cycle; scalable CMOS process; CMOS technology; Circuits; Difference equations; Image processing; Neural network hardware; Neural networks; Neurons; Transconductance; Very large scale integration; Voltage;
Conference_Titel :
Custom Integrated Circuits Conference, 1990., Proceedings of the IEEE 1990
Conference_Location :
Boston, MA
DOI :
10.1109/CICC.1990.124807
