5 GHz phase locked loop with auto band selection

A 5 GHz phase locked loop (PLL) with auto band selection (ABS) is presented. This paper proposes an auto-band selection circuit to control the frequency drifting problem caused by variation of technology process and temperature. The PLL consists of a phase-frequency detector (PFD), a charge pump (CP), a voltage control oscillator (VCO), an auto band selection (ABS), and a pulse-swallow divider. In the pulse swallow divider, this work adopts true single phase clock DFF to operate on high frequency region and save the circuit area and power. The simulation result shows the feasibility of the PLL with the proposed wide tuning range VCO and the auto band selection. The performance of the proposed PLL is also summarized. The proposed PLL is designed with TSMC 0.18 mum CMOS 1P6M technology process and 1.8 V power supply.