DocumentCode
2324924
Title
Three-level AND-OR-XOR network synthesis: A GA based approach
Author
Pradhan, Sambhu Nath ; Kumar, M. Tilak ; Chattopadhyay, Santanu
Author_Institution
Dept. of E & ECE, IIT Kharagpur, Kharagpur
fYear
2008
fDate
Nov. 30 2008-Dec. 3 2008
Firstpage
574
Lastpage
577
Abstract
In this paper we present a heuristic based on Genetic Algorithm to realize multi-output Boolean function as three-level AND-OR-XOR networks along with area power trade-off. All the previous works dealt with the minimization of number of product terms only in the two sum-of-product-expressions representing a Boolean function during AND-OR-XOR network synthesis. To the best of our knowledge this is the first ever effort to incorporate total power, that is, dynamic and leakage power along with the area (in terms of number of product terms) during three-level AND-OR-XOR network synthesis. Our synthesis process gives lesser number of product terms compared to those reported in the literature. It also enumerates the trade-offs present in the solution space for different weights associated with area, dynamic and leakage power of the resulting circuit.
Keywords
Boolean functions; genetic algorithms; logic gates; AND-OR-XOR network synthesis; AND-OR-XOR three level network; genetic algorithm; multioutput Boolean function; sum-of-product-expressions; Boolean functions; Circuit synthesis; Design methodology; Energy consumption; Genetic algorithms; Logic devices; Minimization methods; Network synthesis; Partitioning algorithms; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2008. APCCAS 2008. IEEE Asia Pacific Conference on
Conference_Location
Macao
Print_ISBN
978-1-4244-2341-5
Electronic_ISBN
978-1-4244-2342-2
Type
conf
DOI
10.1109/APCCAS.2008.4746088
Filename
4746088
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