Random address 32×32 programmable analog vector-matrix multiplier for artificial neural networks

A randomly addressable and programmable 32×32 analog vector-matrix multiplier was designed and fabricated using a standard 2 μm p-well CMOS technology. Fully differential random address decoders are used for input and output multiplexing and for writing capacitively stored weights to the multiplier sites. Weight storage measurements show the double capacitive storage approach can have a 1% accuracy at 90°C. The multiplier has been characterized at DC values, and has demonstrated good weight retention at high temperatures. A multiplier total harmonic distortion of 1 to 2% has been measured for expected voltage input ranges