Using clock gating technique for energy reduction in portable computers

Today, Power has become a primary consideration during hardware designs, and is critical in computer systems especially for portable devices for the need of higher performance and more functionality; this requires techniques for energy reduction. Many techniques are used for energy reduction such as, dynamic power management, pipelining, transistor sizing, and clock gating. Clock-gating is the most common technique for reducing microprocessors power. This technique is widely used in digital circuits, and forms the basis of many of the other power reduction techniques; clock-gating implementation becomes an emergency-function, if the CPU is about to overheat, it´s means that the CPU is stopped for some cycles and then is working for some cycles based on the supply voltage control, the CPU will consume less energy per period which reduces the total power usage of a program. This paper presents a hardware design of the clock gating technique, which enables the CPU to reduce the supply voltage accompanied with the clock frequency, based on its workload variation, which leads to a possible reduction in power requirements. Spice simulation results confirm and verify the theoretical idea and successful hardware operations.