Design centering scheme for robust SRAM cell design

In this paper, a statistical approach for the optimal design of 6-T FinFET based SRAM cells considering the statistical distributions of gate length and silicon thickness of its transistors is presented. The corresponding statistical correlations of these two parameters are also considered. In this method, proper back-gate voltages for the SRAM transistors which maximize the yield against read, write, access and hold errors are determined. To assess the efficiency of the approach, the approach is applied to a 45 nm FINFET technology. The use of Monte-Carlo simulations shows the effectiveness of the method for increasing the yield of the FinFET SRAM cells. The proposed scheme is general and may be applied to other circuits.