A power-gating scheme for CAL circuits using single-phase power-clock

This paper presents a power-gating scheme for CAL (clocked adiabatic logic) circuits to reduce energy loss during idle state. A transmission gate is used as the power-gating switch. It is inserted between the single-phase power-clock and virtual power-clocks to detach power-gated CAL logic blocks during idle periods. The 8-bit full adders based on the CAL circuits are used to verify the proposed power-gating technique. All circuits are simulated using the BSIM3V3 models of TSMC 0.18 mum CMOS technology. Energy loss can be reduced greatly by shutting down idle adiabatic logic blocks.