DocumentCode
2326388
Title
Block implementation of fault-tolerant LMS adaptive FIR filters
Author
Lin, Liangkung ; Redinbo, G. Robert
Author_Institution
Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA
fYear
1993
fDate
27-29 Oct 1993
Firstpage
17
Lastpage
24
Abstract
Adaptive FIR filters are widely used in a variety of modern digital signal processing application, and with the advancement in VLSI technology, it is now feasible to build fairly complicated multiprocessor systems which can provide the necessary computational power required by some highly demanding real-time signal processing applications. The increased computational power of such systems also makes fault tolerance an even more important issue that needs to be addressed carefully, because a single hardware failure can easily render the whole compuational results useless. Algorithm-based fault tolerance (ABFT), recently developed as an effective high level fault-tolerant technique, employs, in addition to the normal outputs, parity numbers that are related to the outputs. These parities can be used to concurrently detect, and in some cases correct, errors caused by hardware failures. A highly efficient implementation of the encoding scheme based on the weighted checksum code is proposed. It is particularly suitable for block adaptive signal processing, and the computational efficiency of this method is compared with that of the more general weighted checksum code
Keywords
adaptive filters; VLSI technology; algorithm based fault tolerance; block adaptive signal processing; computational efficiency; computational power; digital signal processing; encoding; error correction; error detection; fault-tolerant LMS adaptive FIR filters; multiprocessor systems; parity generation; real-time signal processing; single hardware failure; weighted checksum code; Adaptive signal processing; Digital signal processing; Fault tolerance; Finite impulse response filter; Hardware; Least squares approximation; Multiprocessing systems; Real time systems; Signal processing algorithms; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance in VLSI Systems, 1993., The IEEE International Workshop on
Conference_Location
Venice
ISSN
1550-5774
Print_ISBN
0-8186-3502-9
Type
conf
DOI
10.1109/DFTVS.1993.595607
Filename
595607
Link To Document