Title :
A CMOS adiabatic inverter operating with a single clock power supply to reduce non-adiabatic loss
Author :
Garcia, J.C. ; Nelson, Juan A Montiel ; Nooshabadi, Saeid
Author_Institution :
Inst. for Appl. Microelectron., Univ. of Las Palmas de Gran Canaria, Las Palmas
fDate :
Nov. 30 2008-Dec. 3 2008
Abstract :
This paper presents the design of a low energy CMOS adiabatic inverter (Ib-driver). The proposed Ib-driver structure uses complementary input, output and a dual-rail structure. When implemented on a 0.13 mum CMOS 1.2 V technology, under the large capacitive loading condition, Ib-driver performs better than the reference adiabatic circuit (sk-driver) in terms of the energy-delay product (21%), with active area which is (34%) lower. Proposed inverter has a full swing for high capacitive loads (20 pF).
Keywords :
CMOS integrated circuits; clock and data recovery circuits; driver circuits; integrated circuit design; invertors; power supply circuits; CMOS adiabatic inverter; Ib-driver structure; capacitance 20 pF; capacitive loading condition; circuit energy-recovery techniques; clock power supply; dual-rail structure; energy-delay product; low-voltage driver circuits; nonadiabatic loss reduction; size 0.13 mum; voltage 1.2 V; CMOS technology; Clocks; Delay; Driver circuits; Energy consumption; Energy efficiency; Integrated circuit interconnections; Inverters; Logic; Power supplies;
Conference_Titel :
Circuits and Systems, 2008. APCCAS 2008. IEEE Asia Pacific Conference on
Conference_Location :
Macao
Print_ISBN :
978-1-4244-2341-5
Electronic_ISBN :
978-1-4244-2342-2
DOI :
10.1109/APCCAS.2008.4746185
